Avicena Announces World's Smallest 1Tbps Optical Transceiver!

Recently, California-based Avicena demonstrated the world's smallest 1Tbps optical transceiver as part of its LightBundle multi-Tbps chip-to-chip interconnect technology at the Supercomputing Conference (SC23) in Denver, Colorado.
Avicena's microLED-based LightBundle architecture supports unprecedented throughput, shoreline density and low power consumption, unlocking processor, memory and sensor performance.
Artificial Intelligence (AI) is driving an unprecedented surge in demand for compute and memory performance, driven by applications such as ChatGPT, which is based on large-scale language models (llm). These complex models have massive and endless demands for computational power and fast access to large amounts of memory, leading to an urgent and growing need for high-density, low-power interconnections between Graphics Processing Units (GPUs) and High Bandwidth Memory (HBM) modules.
At this point in time, HBM modules must be packaged with the GPU because the length of the GPU-memory electronic interconnect is limited to a few millimeters. Subsequent generations of HBMs will require IC shoreline densities of 10 Tbps/mm or more. Meanwhile, traditional optical interconnects based on VCSELs or silicon photonics (SiPh) promise to extend the interconnect range, but struggle to meet size, bandwidth density, power, latency, operating temperature and cost requirements. In contrast, Avicena's microLED-based LightBundle interconnect offers higher bandwidth density, smaller size, lower power and latency, and very low cost.
At Avicena, we are excited to demonstrate the world's most compact 1Tbps transceiver in the shape of a 3mm x 4mm CMOS ASIC using our patented microLED optical interface," said Bardia Pezeshki, Avicena's Founder and CEO. Everyone is talking about SiPh solutions for AI cluster applications. However, for short interconnects at distances of less than 10 meters, we believe an LED-based solution is inherently better suited because of its compact size, higher bandwidth density, lower power consumption and latency, and temperature tolerance up to 150°C."
Avicena's innovation is backed by major investors such as Samsung Catalyst Fund, Cerberus Capital Management, Clear Ventures and Micron Ventures.
Optical interconnect technology has the potential to improve chip-to-chip and rack-to-rack performance," said Marco Chisari, head of Samsung's Semiconductor Innovation Center. With an ever-extending roadmap of multi-Tbps capacity and sub-PJ/bit power efficiency, Avicena's innovative LightBundle interconnect can enable the next era of AI innovation, paving the way for more powerful models and a wide range of AI applications that will shape the future."
The LightBundle interconnect architecture is based on innovative GaN microLED arrays that utilize the microLED display ecosystem and can be integrated directly onto compact, high-performance CMOS ICs. This enables dense, low-power IO across the entire area of the IC for unprecedented shoreline density. Each microLED array is connected to a matching CMOS-compatible PD array via a multi-core fiber optic cable.
The modular LightBundle platform scales to tens of Tbps interconnections with a shoreline density of 10 Tbps/mm. Rob Kalman, co-founder and CTO of Avicena, noted, "We've previously demonstrated microLEDs at 10 Gbps per channel and tested the AOs in a 130nm CMOS process. CMOS process and tested the ASIC running 32 channels at less than 1PJ/bit. now we are launching our first ASIC with more than 300 channels at 4Gbps per channel with a total bi-directional aggregate bandwidth of more than 1Tbps. the ASIC is less than 12mm2 in size and contains a complete transceiver including circuits for the optical Tx and Rx arrays, the as well as a high-speed parallel electrical interface and various DFT/DFM functions such as BERT, loopbacks and Open Eye Monitoring (OEM). All key ASIC functions have been validated and we are currently working to improve yields for manufacturing scalability."